View MSM51V17805DSL_5848765.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor msm51v17805d/dsl 1/17 description the msm51v17805d/dsl is a 2,097,152-word 8-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm51v17805d/dsl achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal cmos process. the msm51v17805d/dsl is available in a 28-pin plastic soj or 28-pin plastic tsop. the MSM51V17805DSL (the self-refresh version) is specially designed for lower-power applications. features ? 2,097,152-word 8-bit configuration ? single 3.3 v power supply, 0.3 v tolerance ? input : lvttl compatible, low input capacitance ? output : lvttl compatible, 3-state ? refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (sl version) ? fast page mode with edo, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? cas before ras self-refresh capability (sl version) ? multi-bit test mode capability ? package options: 28-pin 400 mil plastic soj (soj28-p-400-1.27) (product : msm51v17805d/dsl-xxjs) 28-pin 400 mil plastic tsop (tsopii28-p-400-1.27-k) (product : msm51v17805d/dsl-xxts-k) xx indicates speed rank. product family ? semiconductor msm51v17805d/dsl 2,097,152-word 8-bit dynamic ram : fast page mode type with edo msm51v17805d/dsl-70 70 ns 124 ns 84 ns 288 mw 360 mw family access time (max.) cycle time (min.) standby (max.) power dissipation msm51v17805d/dsl-50 t rac 50 ns 35 ns t aa 25 ns 20 ns t cac 13 ns 20 ns t oea 13 ns msm51v17805d/dsl-60 60 ns 104 ns 324 mw 30 ns 15 ns 15 ns operating (max.) 1.8 mw/ 0.72 mw (sl version) preliminary e2g0129-17-61 this version: mar. 1998
? semiconductor msm51v17805d/dsl 2/17 pin configuration (top view) 3 4 5 9 10 11 12 13 dq2 dq3 dq4 a10r a0 a1 a2 a3 26 25 24 20 19 18 17 16 dq7 dq6 dq5 a8 a7 a6 a5 a4 2 dq1 27 dq8 1 v cc 28 v ss 28-pin plastic soj 3 4 5 9 10 11 12 13 26 25 24 20 19 18 17 16 2 27 1 28 28-pin plastic tsop (k type) 6 we 23 cas 23 8 nc 21 a9 21 6 8 7 ras 22 oe 22 7 14 v cc 15 v ss 14 15 dq2 dq3 dq4 a10r a0 a1 a2 a3 dq1 v cc we nc ras v cc dq7 dq6 dq5 a8 a7 a6 a5 a4 dq8 v ss cas a9 oe v ss pin name function a0 - a9, a10r address input ras row address strobe cas column address strobe dq1 - dq8 data input/data output oe output enable we write enable v cc power supply (3.3 v) v ss ground (0 v) note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin.
? semiconductor msm51v17805d/dsl 3/17 block diagram timing generator refresh control clock column address buffers internal address counter row address buffers row deco- ders word drivers memory cells sense amplifiers column decoders i/o controller i/o selector output buffers input buffers on chip v bb generator v cc dq1 - dq8 cas we a0 - a9 10 10 8 8 8 8 88 11 10 oe ras v ss 1 a10r
? semiconductor msm51v17805d/dsl 4/17 electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg ?.5 to 4.6 50 1 0 to 70 ?5 to 150 rating ma w ? ? parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 3.3 0 typ. parameter 3.0 0 2.0 ?.3 min. 3.6 0 v cc + 0.3 0.8 max. (ta = 0? to 70?) v unit v v v input capacitance (a0 - a9, a10r) input capacitance ( ras , cas , we , oe ) output capacitance (dq1 - dq8) c in1 symbol c in2 c i/o 5 7 7 max. pf unit pf pf parameter (v cc = 3.3 v ?.3 v, ta = 25?, f = 1 mhz) typ.
? semiconductor msm51v17805d/dsl 5/17 dc characteristics parameter symbol condition msm51v17805 d/dsl-50 msm51v17805 d/dsl-60 msm51v17805 d/dsl-70 (v cc = 3.3 v ?.3 v, ta = 0? to 70?) i oh = ?.0 ma output high voltage i ol = 2.0 ma output low voltage 0 v v i v cc + 0.3 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o v cc ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) dq = enable average power cas before ras supply current ( cas before ras refresh) average power ras 0.2 v, supply current cas 0.2 v ( cas before ras v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i ccs 3 v cc ?.2 v min. max. min. max. min. max. unit note ras cycling, 2.4 0 ?0 ?0 v cc 0.4 10 10 100 2 0.5 100 100 300 5 2.4 0 ?0 ?0 v cc 0.4 10 10 90 2 0.5 90 90 300 5 2.4 0 ?0 ?0 v cc 0.4 10 10 80 2 0.5 80 80 300 5 200 200 200 v v m a m a ma ma ma ma m a ma 1, 2 1, 2 1, 2 1, 5 1 1 m a 1, 5 t rc = 62.5 m s, average power cas before ras , supply current t ras 1 m s (battery backup) i cc10 300 300 300 m a 1, 4, ras = v il , average power cas cycling, supply current t hpc = min. (fast page mode) i cc7 100 90 80 ma 1, 3 5 self-refresh) notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih . 4. v cc C 0.2 v v ih v cc + 0.3 v, C0.3 v v il 0.2 v. 5. sl version.
? semiconductor msm51v17805d/dsl 6/17 ac characteristics (1/2) parameter msm51v17805 d/dsl-60 msm51v17805 d/dsl-70 msm51v17805 d/dsl-50 (v cc = 3.3 v ?.3 v, ta = 0? to 70?) note 1, 2, 3, 12, 13 random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from cas precharge cas to data output buffer turn-off delay time transition time ras precharge time ras pulse width ras pulse width (fast page mode with edo) ras hold time cas pulse width cas hold time ras to cas delay time ras to column address delay time cas to ras precharge time row address set-up time row address hold time column address set-up time column address hold time column address to ras lead time access time from oe oe to data output buffer turn-off delay time refresh period ras hold time referenced to oe unit min. max. min. max. ras hold time from cas precharge symbol t rc t rwc t hpc t hprwc t rac t cac t aa t cpa t cez t t t rp t ras t rasp t rsh t cas t csh t rcd t rad t crp t asr t rah t asc t cah t ral t oea t oez t ref t roh t rhcp note min. max. output low impedance time from cas t clz cas precharge time (fast page mode with edo) t cp 4, 5, 6 4, 5 4, 6 4 7, 8 5 6 4 7 4 3 14 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 84 110 20 58 0 0 1 30 50 50 7 7 7 35 11 9 5 0 7 0 7 25 0 7 30 50 13 25 30 13 50 10,000 100,000 10,000 37 25 13 13 32 124 160 30 78 0 0 1 50 70 70 13 10 13 45 14 12 5 0 10 0 13 35 0 13 40 70 20 35 40 20 50 10,000 100,000 10,000 50 35 20 20 32 104 135 25 68 0 0 1 40 60 60 10 10 10 40 14 12 5 0 10 0 10 30 0 10 35 60 15 30 35 15 50 10,000 100,000 10,000 45 30 15 15 32 refresh period (sl version) t ref ms 128 128 128 data output hold after cas low we to data output buffer turn-off delay time ras to data output buffer turn-off delay time t doh t wez t rez 7, 8 7 ns ns ns 5 5 5 oe hold time from cas (dq disable) t cho ns 5 5 5 0 0 13 13 0 0 20 20 0 0 15 15
? semiconductor msm51v17805d/dsl 7/17 ac characteristics (2/2) msm51v17805 d/dsl-60 msm51v17805 d/dsl-70 msm51v17805 d/dsl-50 write command pulse width write command to cas lead time write command to ras lead time data-in set-up time cas to we delay time ras to we delay time column address to we delay time ras to cas hold time ( cas before ras ) cas active delay time from ras precharge data-in hold time write command hold time oe command hold time oe to data-in delay time (v cc = 3.3 v ?.3 v, ta = 0? to 70?) note 1, 2, 3, 12, 13 write command set-up time t wp t cwl t rwl t ds t cwd t rwd t awd t chr t rpc t dh t wch t oeh t oed t wcs min. max. parameter symbol unit note min. max. min. max. ras to cas set-up time ( cas before ras )t csr we to ras precharge time ( cas before ras ) t wrp we hold time from ras ( cas before ras )t wrh ras to we set-up time (test mode) t wts cas precharge we delay time t cpwd ras to we hold time (test mode) t wth 11 10 10 10 11 10 10 10 10 10 10 10 0 34 79 49 5 10 5 10 10 15 0 54 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 7 0 30 67 42 5 10 5 7 7 13 0 47 10 10 10 10 10 0 44 94 59 5 10 5 13 13 20 0 64 ras pulse width t rass 14 100 m s 100 100 ( cas before ras self-refresh) ras precharge time t rps 14 110 ns 90 130 ( cas before ras self-refresh) cas hold time t chs 14 ?0 ns ?0 ?0 ( cas before ras self-refresh) read command set-up time read command hold time read command hold time referenced to ras t rcs t rch t rrh 9 9 ns ns ns 0 0 0 0 0 0 0 0 0 we pulse width (dq disable) t wpe ns oe command hold time t och ns oe precharge time t oep ns 10 7 10 10 7 13 10 7 10 10 7 10 10 7 13 10 7 13
? semiconductor msm51v17805d/dsl 8/17 notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 2 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 1 ttl load and 100 pf. the output timing reference levels are v oh = 2.0 v and v ol = 0.8 v. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t cez and t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 12. the test mode is initiated by performing a we and cas before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is generated. the test mode specified in this data sheet is a 2-bit parallel test function. ca9 is not used. in a read cycle, if all internal bits are equal, the dq pin will indicate a high level. if any internal bits are not equal, the dq pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operating state by performing a ras -only refresh cycle or a cas before ras refresh cycle. 13. in a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. these parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 14. only sl version.
? semiconductor msm51v17805d/dsl 9/17 "h" or "l" ras cas v ih v il v ih v il dq v ih v il address v ih v il we v ih v il oe v ih v il t rc t ras t rp t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t ds t dh valid data-in t wp t ral open t rwl t cwl timing waveform read cycle write cycle (early write) "h" or "l" ras cas v ih v il v ih v il dq v oh v ol address v ih v il we v ih v il oe v ih v il t rc t ras t rp t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t cez open t clz valid data-out t rez e2g0102-17-41o
? semiconductor msm51v17805d/dsl 10/17 read modify write cycle "h" or "l" ras cas v ih v il v ih v il dq v i/oh v i/ol address v ih v il we v ih v il oe v ih v il t rwc t ras t rp t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh
? semiconductor msm51v17805d/dsl 11/17 fast page mode read cycle (part-1) fast page mode read cycle (part-2) v ih ras address we dq cas oe v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cp t cah t asc t rad t rcs t rch t rac t aa t cac t clz t wez t oea valid data-out valid data-out valid data-out t rah t asr t cah t asc t cah t asc t cac t aa t doh t cez t cpa t aa t cac t rcs t wpe t rhcp e e e e e e e e v ih ras address we dq cas oe v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t aa t rrh t cac t clz t cpa t oea valid data-out valid* data-out t rah t asr t cah t asc t cah t asc t rac valid data-out t aa t cac t doh valid* data-out t cac t rez t oez t oez t cho t och t aa t oea t oep t oep t oea * : same data, t cp t rhcp
? semiconductor msm51v17805d/dsl 12/17 fast page mode write cycle (early write) fast page mode read modify write cycle v ih ras address we dq cas oe v il v ih v il v ih v il v ih v il v ih v il v ih v il t asr row column t crp t rp t rasp t cas t csh t rah column column t rcd t cp t cas t cas t hpc t cp t hpc t asc t cah t cah t cah t asc t asc t rad "h" or "l" t dh t ds t wch valid data-in t ds t dh t ds t dh t wch t wch t rsh valid data-in valid data-in t wcs t wcs t wcs e e e e e e e e v ih ras address we dq cas oe v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t asr row column t rasp t cwd t rah column t rcd t cp t asc t cah t cpa t asc t rad t rwd "h" or "l" valid data-out t oez t oed t ds t wp t awd t rcs t cwd t rwl t cac t awd t rac t wp t clz t dh t oeh valid data-in t oea valid data-out t oez t oed t cac t dh t oeh valid data-in t oea t clz t ds t aa t aa t rcs t cah t cpwd t hprwc t crp t cwl
? semiconductor msm51v17805d/dsl 13/17 ras -only refresh cycle cas before ras refresh cycle f p q r s \ ] ^ k l m v ih v il ras t rp cas v ih v il v ih v il we v v "h" or "l" t rc t ras t rpc t chr t rp t rpc t cp t csr t wrp t wrh t cez t wrp open ol oh dq note: oe , address = "h" or "l" : f m n o p q r s k ] ^ _ v ih v il ras t t rp t cas v ih v il v ih v il address ras "h" or "l" rc note: we , oe = "h" or "l" t crp t rpc t asr t rah row v oh v ol dq t cez open
? semiconductor msm51v17805d/dsl 14/17 hidden refresh read cycle hidden refresh write cycle v ih ras address we dq cas oe v il v ih v il v ih v il v ih v il v ih v il v ih v il "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ds t wp t wch t dh valid data-in t wcs ras cas address oe v ih v il v ih v il v ih v il v ih v il "h" or "l" we v ih v il dq v oh v ol t rc t rc t ras t rp t ras t rp t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t clz t oez valid data-out open t cez t rez
? semiconductor msm51v17805d/dsl 15/17 cas before ras self-refresh cycle f o p q r s \ ] ^ _ k l m v ih v il ras cas v ih v il v ih v il we v v "h" or "l" t rc t ras t chr t rp t rpc t cp t csr t wts t wth t off open ol oh dq note: oe , address = "h" or "l" only sl version test mode initiate cycle v ih v il ras cas v ih v il t ras "h" or "l" v oh v ol v ih v il open t rc t wth t rpc t wts t cp t csr t chr t off note: oe , address = "h" or "l" t rp we dq
? semiconductor msm51v17805d/dsl 16/17 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj28-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.30 typ. mirror finish
? semiconductor msm51v17805d/dsl 17/17 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop ii 28-p-400-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.51 typ. mirror finish

▲Up To Search▲

Price & Availability of MSM51V17805DSL

	To Download MSM51V17805DSL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .